I am an electronic engineering professional with an entrepreneurial spirit. I have a strong interest in electronic design, methodology, electronic design automation (EDA), and EDA tool development.
I have participated in a wide range of successful digital ASIC, mixed-signal ASIC and FPGA design projects for telecom, DSP, sensor, and image processing applications. I have in-depth experience in methodologies based on VHDL, Verilog, SystemVerilog, SystemC, and MyHDL.
Today I work as an independent consultant.
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Many things in HDL-based design are not the way I think they ought to be. I have complained a lot about this in the past. With MyHDL, I turn that negative energy into something positive. Instead of complaining, I now implement it the way I want!
I am happy to see that more and more people find MyHDL useful. There is a lot of working silicon designed with MyHDL, and I intend to build further on that momentum.
Urubu is my latest open source project. It is a micro CMS for static websites. It allows me to (finally) develop and maintain websites in the way I want to. For the rationale behind this project, read I don't like blogs (Introducing Urubu).
Sigasi is a young company that develops a next-generation VHDL and Verilog design environment. I am advising them both on business development and technical matters.
Sigasi's founders have a lot of experience with modern integrated development environments such as Eclipse. Their idea is to develop a similar tool for VHDL-based hardware development. I must say this opened a new world to me, and I'm now convinced this is the way forward for HDL-based design.
The differentiating technology behind Sigasi HDT is that it contains an ultra-fast parser and analyzer. This means that at any given moment during development, the tool understands your project as a VHDL design instead of a bunch of files. This means that any development task can be enhanced with design intelligence, which can boost productivity tremendously.
For example, consider navigation. By simply hovering over an identifier, you get instant feedback about its declaration and you can jump to it immediately.
Another example is error reporting. You don't just get feedback about syntax errors, but also about conceptual problems such as incomplete sensitivity lists, missing signal declarations, and unused variables or signals. Moreover, the tool can automatically fix such errors.
One more example is autocompletion. Of course, traditional template-based methods are available, but the tool goes much further using its knowledge of the design. For example, when you start typing an instantiation, it can let you choose between all matching entities, and fill in the port map automatically.
Another sophisticated functionality is automated refactoring, which is a modern software technique to improve code by restructuring it without modifying functionality. The simplest (but incredibly useful) example is Rename, which is not based on string equality within one file, but on object identity in the whole design.
In short, if you are designing in VHDL, I strongly advise you to take a look at Sigasi!
I maintain a number of websites for my activities:
The MyHDL website is the main website for MyHDL info.
The MyHDL development website has the info for MyHDL developers.
Sigasi / Jan on HDL is a blog about HDL design, hosted by Sigasi.
Urubu is the website for the Urubu static website generator.
Music is dedicated to my musical activities.
Opinions (in Dutch) is a website with my opinions about politics and economics. This website is in Dutch as that is my native languages.
Technical and business consultancy
I have a lot of technical experience in VHDL, Verilog, HDL-based design, verification, synthesis, and in ASIC, FPGA and SoC design. My specialty is methodology, possibly supported by dedicated EDA tool development.
My business and entrepreneurial expertise is available to companies in the domains of electronic design and EDA. For these activities I often cooperate with SO Kwadraat, which is an organization dedicated to the creation of start-ups in Flanders.
MyHDL-based ASIC and FPGA design
I am available for contract work on MyHDL-based ASIC and FPGA designs. You can find out more about MyHDL here. As I am the creator of MyHDL and as I have many years of experience in digital design, you will get the best possible service.
Commercial support for MyHDL
I offer commercial support for the open-source MyHDL project.
Commercial support for Urubu
In 1985, I obtained a degree in electronics engineering at the Catholic University of Leuven, Belgium. After graduating, I worked as a research assistant at the Inter-university Micro-Electronics Center (IMEC) in Leuven, Belgium, from 1985 to 1988, and at the University of São Paulo, Brazil, from 1988 to 1990.
From 1990 to 1991, I worked at Alcatel Bell in Antwerp, Belgium as a design engineer of broadband telecommunications ASICs. From this period dates my first experience with logic synthesis and the RTL design methodology.
In 1992, I co-founded Easics, a hardware design services company. At Easics, I have been responsible for design methodology and in-house tool development. In May 2000, Easics was acquired by TranSwitch, a supplier of VLSI solutions to the communications equipment industry. In November 2002, I left Easics to become an independent developer and consultant. In 2005, a team of employees acquired Easics through an MBO.
Since 2006 I am working as a business development and technical consultant. In 2006 I co-founded Mephisto Design Automation, a company that developed an advanced analog design automation tool. Since 2008 I am working with Sigasi, a company that makes a modern VHDL design productivity tool.